About Department
Department of Electronics Engineering (VLSI Design and Technology) was started in the year 2023. The department offers 4 years Under Graduate (UG). The student intake for the UG programme is 60. The curriculum and syllabus for the programmes offered in the department are designed as per the Regulation 2022 of the autonomous system. The curriculum is designed to achieve a balance between depth of knowledge acquired through specialization and breadth of knowledge gained through exploration. The undergraduate degree courses offered by the department provide a comprehensive foundation in the core topics of electronics coupled with areas of specialization relevant to emerging engineering challenges of VLSI. The curriculum has been designed to create professional electronics engineers, who can serve in the fields of core electronics engineering, VLSI and other related fields.
Vision
To emerge as a distinguished center of academic excellence, offering exceptional education in Electronics Engineering, with a distinct focus on VLSI design and advanced research.
Mission
The PEOs of UG Programmes
Programme Outcomes (POs)
Programme Specific Outcomes (PSOs)
Engineering Graduates will be able to:
Department Contact
Professor & Head
AICTE Faculty ID:1-461790295 ;| College ID: KSREI02
LinkedIn Profile | IRINS Profile| ProfileMail-ID: [email protected]
Dr. T. Baranidharan has more than 18 years of teaching experience. He graduated with a B.E. degree in Electronics and Instrumentation Engineering from shanmugha college of Engineering, Bharathidasan University, Tiruchirappalli in the year 2003. He completed his post-graduation in Applied Electronics from Thanthai Periyar Government Institute of Technology at Anna University in 2005. He received his Ph.D. from Anna University, Chennai in 2013. He published 13 papers in reputed international journals. He presented several papers in various International & National Conferences. He is a recognized research supervisor at Anna University Chennai. Currently, 01 candidates have completed their Ph.D. under his guidance and 4 Ph.D. research scholars are pursuing currently. He organized several seminars, workshops, and conferences.
2025-26 - Click here
Associate Professor & Vacation Co-ordinator
VLSI Design & Technology
Assistant Professor
VLSI Design & Technology (Low power VLSI)
Assistant Professor
VLSI Design & Technology (VLSI Testing)
Assistant Professor
VLSI Design & Technology (Low Power VLSI)
Assistant Professor
VLSI Design & Medical Image Processing
Assistant Professor
VLSI Design & Technology
Lab Technician
Lab Technician
Programmer
Lab Attender
Under-Graduate - Electronics Engineering (VLSI Design and Technology)
| S.No | Name of the Faculty | Name of the Course & Module | Objective | Innovation in Teaching and Learning(Experiential Learning/Participative Learning) | Web page content Link-Proof |
|---|---|---|---|---|---|
| 1. | Dr.S.Pradeep | 60 EV 302 - Circuit Analysis | To apply and verify Thevenin's and Norton's theorems by simplifying complex circuits and comparing the calculated values of voltage and current with those obtained through simulation | Simulation | Click Here |
| 2. | Mr.T.Rajavenkatesan | 60 EV 301 - Electronic Circuits | The objective of using EdPuzzle for a "voltage series feedback amplifier" topic is to actively engage students with a video lesson by embedding interactive questions, ensuring they comprehend key concepts. | Ed-Puzzle | Click Here |
| 3. | Mrs.C.Saranya | 60 EV 502 - VLSI and Chip Design | The objective of a seminar on "RTL to GDS" is to provide a comprehensive understanding of the entire digital chip design flow, from the initial Register-Transfer Level (RTL) design to the final GDSII layout file used for fabrication. | Seminar | Click Here |
| 4. | Mr.D.Poorna Kumar | 60 EV 303 - Digital System Design | To demonstrate the fundamental principles of logic gates (AND, OR, NOT) through a role-play, where each participant embodies a gate and collectively processes inputs to produce a final output, illustrating how these basic components form the building blocks of digital circuits. | Role Play | Click Here |
Circuit Analysis
VLSI and Chip Design
Digital System Design
Digital Signal Processing
| S.No. | Date | Name of Course | Industry Association |
|---|---|---|---|
| 1. | 02.07.2025 | 60 EV E13 & ASIC Synthesis and STA | VLSI Mentors, Bengaluru |
| Duration of Training/Internship | Credits | |||||
|---|---|---|---|---|---|---|
| 2 Weeks | 1 | |||||
| 3 Weeks | 2 | |||||
| 8 Weeks& above | 3 | |||||
| S.No. | Academic Year | Name of the Industry | Duration | No.of Students | ||
|---|---|---|---|---|---|---|
| 1. | 2024-25 | Mspand Technologies Pvt.Ltd, Theni | 30.12.2024-11.01.2025 | 15 | View | |
| 2. | 2024-25 | Indira Gandhi Centre for Atomic Research [IGCAR],Kalpakkam | 20.05.2025-30.06.2025 | 7 | View | |
| S.No. | Academic Year | Name of the Industry | Duration | No.of Students | |
|---|---|---|---|---|---|
| 1. | 2025-26 | Mspand Technologies Pvt.Ltd, Theni | 23.06.2025-11.07.2025 | 15 | View |
| 2. | 2025-26 | VLSI Mentors | 20.06.2025-25.07.2025 | 30 | View |

| S.No. | Particulars | Count |
|---|---|---|
| 1. | Ph.D. Doctorates | 3 |
| 2. | Ph.D. Supervisors | 1 |
| 3. | Ph.D. Pursuing | 2 |
| 8. | Ph.D. Completed | - |
| S.No. | Academic Year | Book Chapters | Journals | Conference | ||
|---|---|---|---|---|---|---|
| National | International | National | International | |||
| 1. | 2025-26 | - | - | 1 | - | 2 |
| 2. | 2024-25 | 4 | 2 | 5 | - | 11 |
| S.No. | Academic Year | Patents | Copyrights | |||
|---|---|---|---|---|---|---|
| Filed | Published | Granted | Filed | Granted | ||
| 1. | 2025-26 | 1 | - | - | - | - |
| 1. | 2024-25 | 13 | 12 | 2 | - | - |
| S.No. | Academic Year | Name of Faculty (Chief Consultant) | Client Organization | Title of the Project | Duration | Amount received(in Rupees) |
|---|---|---|---|---|---|---|
| 1. | 2024-25 | Dr.S.Gomathi | Arunai Creations | Sewing Machine board Automation and error correction service | 18.10.2024 to 20.10.2025 | 50,000 |
| 2. | 2024-25 | Dr.S.Gomathi | VSAN Electricals | VLSI Design of an Advanced Capacitive Proximity Sensor for Industrial Automation | 02.01.2025 to 18.03.2025 | 1,20,000 |
| S. No. | Date of Signing | Name of the Company | Validity |
|---|---|---|---|
| ACADEMIC YEAR (2024 – 2025) | |||
| 1 | 01.11.2024 | VLSI Mentors,Bangalore | 3 Years |
| 2 | 18.10.2024 | Mspand Technologies Pvt.Ltd,Theni | 3 Years |
| S.No. | Academic Year | Number of Events | |
|---|---|---|---|
| 1. | 2025-26 | 2 | |
| 2. | 2024-25 | 12 |
S2S CLUB (Student 2 Skill)
1. S.B.Tamilraja
2. S.Dharanisri
3. M.Sathyajeeva
4. M.Suriya Prasanth
5. D.Tharun
6. S.Chindu Sri
| S.No. | Academic Year | Number of Events | |
|---|---|---|---|
| 1. | 2025-26 | 1 | |
| 2. | 2024-25 | 2 |
CSSR CLUB (Centre For Silicon System Research )
1. M.Deepasri
2. S.Y.Omganesh
3. R.Vinoth
4. G.S.Harshaprabha
5. P.V.Sudharson
6. S.Kalaimagal
| S.No. | Year | Number of Events | |
|---|---|---|---|
| 1. | 2025-26 | 1 | View |
| 2. | 2024-25 | 2 | View |
| S.No. | Date | Name of industry | No.of Students Visited |
|---|---|---|---|
| 1. | 20.09.2024 | ISRO, Bengaluru | 50(2023-27 Batch) |
| 2. | 20.09.2024 | Tessolve Semiconductor Pvt.Ltd, Bengaluru | 50(2023-27 Batch) |